Microsystems Technology Office (MTO)

Precise timing is essential across DoD systems, including communications, navigation, electronic warfare, intelligence systems reconnaissance, and system-of-systems platform coordination, as well as in national infrastructure applications in commerce and banking, telecommunications, and power distribution. Improved clock performance throughout the timing network, particularly at point-of-use, would enable advanced collaborative capabilities and provide greater resilience to disruptions of timing synchronization networks, notably by reducing reliance on satellite-based global navigation satellite system (GNSS) timing signals. More

State-of-the-art magnetometers are used for diverse civilian and DoD applications, among them biomedical imaging, navigation, and detecting unexploded ordnance and underwater and underground anomalies. Commercially available magnetometers range from inexpensive Hall probes to highly sensitive fluxgate and atomic magnetometers to high-precision Superconducting Quantum Interference Device (SQUID) and Spin Exchange Relaxation Free (SERF) magnetometers. More

Atom-based devices have proven to be the most accurate means of measuring the physical world. Two areas of great promise are the ability to measure frequency with optically probed trapped atom clocks as well as optically cooled atom interferometer inertial sensors. Together, they could form the basis of a fully autonomous navigation and timing system, free from GPS. Integration of these laboratory based quantum devices into a practical size, weight, and power has proven challenging. Furthermore, replicating these devices at laboratory scale is still resource intensive. More

The Automatic Implementation of Secure Silicon (AISS) program aims to ease the burden of developing secure chips. AISS seeks to create a novel, automated chip design flow that will allow security mechanisms to scale consistently with the goals of a chip design. The target design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security trade-off. The target system on chip (SoC) – will be automatically generated, integrated, and optimized, and will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. More

It can cost up to $100 million and take more than two years for a large team of engineers to design custom integrated circuits for specific tasks, such as synchronizing the activity of unmanned aerial vehicles or the real-time conversion of raw radar data into tactically useful 3-D imagery. This is why Defense Department engineers often turn to inexpensive and readily available general-purpose circuits, and then rely on software to make those circuits run the specialized operations they need. More