SHIELDER | STTR

OUSD (R&E) critical technology area(s): Advanced Materials, Microelectronics, Materials/Processes

Objective: Develop and demonstrate novel nanofabrication hard-mask materials that exhibit substantially improved plasma etch resistance, enabling the implementation of extreme high-aspect-ratio structures with excellent pattern-transfer fidelity, minimal sidewall roughness, and precise dimensional control. Proposed solutions should overcome the fundamental limitations of conventional lithography masks in a scalable fabrication environment by creating next-generation technologies capable of delivering high-resolution nanoscale features encountered across semiconductor, photonic, MEMS, and quantum device platforms.

Description: Next-generation defense-relevant microsystem technologies, such as 3D integrated circuits, high-density memory arrays, MEMS inertial sensors and RF filters, and integrated photonic devices, rely on the precise manufacturing of extreme high-aspect-ratio features within a chip [1-3]. Furthermore, emerging architectures for multiferroic memory and logic components, such as those being pioneered under DARPA's Fast and Curious program [4], stand to benefit immensely from novel process flows capable of delivering deep trenches with ultra-low line-edge roughness. As critical dimensions of these devices continue to shrink to improve performance or reduce size and cost, the ability to accurately transfer lithographic patterns into underlying substrates (such as silicon) via aggressive plasma etching has become a primary manufacturing bottleneck.

Current state-of-the-art (SOTA) hard masks predominantly utilize thick chemical vapor deposition (CVD) inorganic films (e.g. silicon dioxide, silicon nitride) or sputtered metals. These conventional technologies face fundamental physical limitations at extreme scales. To achieve the necessary etch resistance, standard masks must be deposited with significant thickness, which induces high stress, structural instability, pattern distortion, and reduced feature fidelity during the etch process. Furthermore, conventional metal masks exhibit polycrystalline structures; their inherent grain boundaries erode unevenly under ion bombardment, propagating severe line-edge and sidewall roughness that degrades the electrical and structural integrity of the final device.

This STTR topic seeks highly innovative masking materials that disrupt the current paradigm. The goal is to identify and develop solutions that deliver ultra-high etch selectivity while addressing the weaknesses of current SOTA solutions. Proposed approaches should inherently bypass the degradation mechanisms of traditional masks by utilizing low-dimensional, continuously ordered, inherently grain-free and/or self-regenerating structures to ensure pristine pattern transferring with low line-edge roughness even when subjected to aggressive, high-density plasma [5-7].

Solutions do not have to be limited to silicon processing and may target compound semiconductors, wide-bandgap materials, piezoelectric substrates, ceramics, heterogeneous material stacks or any other microsystems platform relevant to the Department of War (DoW). Compatibility with existing or minimally-modified reactive ion etching (RIE), inductively coupled plasma (ICP), Bosch Deep RIE (DRIE), or related plasma fabrication tools is strongly preferred.

Proposers should identify the underlying physical mechanisms responsible for enhanced pattern-transfer performance and demonstrate a clear path toward scalable manufacturing. Metrics of interest include improvements in etch selectivity, maximum achievable aspect ratio, critical-dimension control, sidewall roughness, mask thickness reduction, process throughput, and compatibility with wafer-scale manufacturing.

Phase I

This topic is soliciting Direct to Phase II (DP2) proposals only. Proposals will be considered for DP2 funding for teams that provide compelling evidence of the feasibility of their novel hard-mask materials at a laboratory or R&D fabrication facility. Proposers must provide data showing that Phase I feasibility has been achieved through prior work. Required documentation includes:

• Etch Selectivity Data: Experimental data demonstrating the successful deposition, synthesis, or transfer of low-stress mask films, alongside measured etch selectivity exceeding 50:1 against target substrates (e.g., silicon or complex oxides) under aggressive dry plasma conditions.
• High-Aspect-Ratio Pattern Transfer: Proof-of-concept fabrication data showing deep pattern transfer into a substrate, achieving an aspect ratio of > 25:1 without significant mask degradation, faceting, or critical dimension (CD) loss.
• Edge Fidelity & Roughness Verification: High-resolution metrology data (e.g., cross-sectional SEM, TEM, or AFM) verifying pristine pattern transfer, specifically demonstrating etched structures with nanometer-scale sidewall roughness (< 5 nm RMS).
• Scalability & Integration Pathway: Initial feasibility data or a substantiated extrapolation demonstrating a viable pathway to scale the masking technology from lab-scale prototypes to wafer-level dimensions (e.g., via CVD, ALD, or scalable continuous transfer methods). Proposers must document how their proposed materials and process flows align with standard commercial fabrication and/or DoW constraints, specifically addressing: CMOS compatibility, thermal budget, vendor/foundry transferability, and any additional constraints imposed by the application of interest.

Phase II

Direct to Phase II (DP2): Develop, integrate, and demonstrate the following:

• Scalable deposition, synthesis, or transfer methodologies for hard-mask materials. Candidate masks must demonstrate an etch selectivity exceeding that of state-of-the-art inorganic films or sputtered metals, e.g., > 150:1 (mask-to-substrate) under aggressive plasma conditions.
• High-fidelity pattern transfer capabilities demonstrating extreme aspect ratios (100:1) without mask failure, critical dimension loss, or top-edge faceting.
• Sub-nanometer dimensional control, with candidate masks demonstrating etched structures with sidewall and line-edge roughness of < 2 nm root-mean-square (RMS).
• Compatibility with standard lithographic workflows. The hard mask itself must be readily patternable (e.g., via secondary chemical plasma or resist) while maintaining extreme resistance to the primary deep-etch plasma.
• Mitigation of unwanted metallic or particulate contamination to levels acceptable for standard semiconductor, MEMS, or photonic device fabrication lines.

Hard mask demonstration must be conducted in a standard cleanroom environment where the process can be scaled to production and which supports the processing of standard-size wafers using commercial Deep Reactive Ion Etching (DRIE) or other Inductively Coupled Plasma (ICP) tools. Patterning performance must be compared between the novel hard mask versus a standard baseline mask material such as silicon dioxide, silicon nitride, or a sputtered metal (e.g., TiN, Cr). The goal is to demonstrate that the novel mask successfully maintains structural integrity in aggressive etch conditions where standard masks fail, e.g., the novel mask maintains CD fidelity and sub-nanometer sidewall smoothness at etch depths that would completely erode or severely facet the standard mask. Compared to standard masks, the proposed solution must deliver a statistically significant reduction in defect propagation and edge roughness.

This DP2 will also require a commercialization and transition plan along with technology development. Throughout the phase, the proposers must collaborate with commercial and military end-users to refine operational requirements and deployment scenarios of their developed solution. Manufacturing and scaling plans for production must also be developed before the end of the program. The final report must also include technology transfer documents outlining planned opportunities for commercial and military applications.

The deliverables for DP2 will include the final prototype mask formulation/process recipe, a comprehensive testing and validation report outlining the final demonstration, the technology transfer plan with commercialization plans, manufacturing and scaling strategy.

DP2 Base milestones for this program should include:

• Month 3: Establish and report baseline parameters for the candidate mask material and develop a comprehensive chemical vapor deposition (or equivalent scalable deposition) process map.
• Month 6: Demonstrate initial solution-based (or alternative scalable) coating and dry etching. Achieve stable precursor formulation, continuous film formation on small-scale substrates, and an initial mask-to-substrate etch selectivity of at least 50:1.
• Month 9: Screen multiple mask candidates and execute the first patterned etch using the down-selected scalable coating method. Demonstrate initial high-aspect-ratio patterning (e.g., > 75:1) with a line-edge roughness of 5 nm or less using a process flow that is scalable to production levels.
• Month 12: Demonstrate process scalability with a target mask-to-substrate etch selectivity of at least 100:1.
• Month 15: Expand process integration for the mask deposition. Achieve strict film thickness uniformity (e.g., less than 10% variation) across intermediate-scale substrates and demonstrate patterning resolution with minimum feature sizes of 100 nanometers or less.
• Month 18: Validate mask performance on alternative, non-standard semiconductor or dielectric substrates. Demonstrate a minimum selectivity of 50:1 on at least two alternative materials and scale the coating process to larger wafer sizes.
• Month 21: Execute integrated, wafer-level processing demonstrations. Show successful transfer or direct integration of the vapor-deposited films and validate extreme etching capabilities on application-specific substrates (e.g., semiconductor devices, MEMS components, photonic structures).
• Month 24: Final Phase II demonstration. Achieve extreme etch selectivity (>150:1), ultra-high aspect ratios (>100:1) on primary semiconductor substrates, and strict dimensional control with a line-edge roughness of 2 nanometers or less.

Upon successful demonstration of the 2D hard-mask technology scale-up, a phase II option may be exercised at DARPA’s discretion to bridge the gap between prototype-scale demonstrations and production-ready Phase III capabilities.

DP2 option milestones include:

• Month 30: Partnership engagement and manufacturing qualification. Finalize commercial-grade manufacturing standards and deliver final commercialization strategy.
• Month 36: Pilot production initiation and Phase III readiness. Demonstrate successful delivery of first evaluation sample batch at production-scale facility.

Phase III dual use applications

Phase III efforts should focus in transitioning the developed hard-mask technology to DoW and commercial semiconductor fabrication facilities. DoW applications include the domestic manufacturing of secure high-density memory, advanced electro-optical components, and high-performance MEMS/RF components for electronic warfare and GPS-denied navigation. Commercially, this technology addresses fundamental physical scaling bottlenecks in the global semiconductor industry. Direct dual-use applications include the production of next-generation 3D semiconductor transistors, multiferroic memory and logic components, high-coherence solid-state quantum devices.

References

[1] Wu, Banqiu, Ajay Kumar, and Sharma Pamarthy. "High aspect ratio silicon etch: A review." Journal of applied physics 108.5 (2010).

[2] Huff, Michael. "Recent advances in reactive ion etching and applications of high-aspect-ratio microfabrication." Micromachines 12, no. 8 (2021): 991.

[3] Tang, Yemin, Amin Sandoughsaz, and Khalil Najafi. "Ultra high aspect-ratio and thick deep silicon etching (UDRIE)." 2017 IEEE 30th International Conference on Micro Electro Mechanical Systems (MEMS). IEEE, 2017.

[4] DARPA Fast and Curious: https://www.darpa.mil/research/programs/fast-and-curious

[5] Esmeraldo Paiva, Aislan, et al. "High Aspect Ratio Nanoscale Pores through BCP-Based Meal Oxide Masks and Advanced Dry Etching." ACS applied materials & interfaces 15.50 (2023): 57960-57969. https://pubmed.ncbi.nlm.nih.gov/37861980/

[6] Bernet, Marc, et al. "Highly selective anisotropic dry etching of smooth SiO2 nanostructures using SF6 plasma and Cr hard mask: Toward sustainable plasma etching." Journal of Vacuum Science & Technology B 44.2 (2026).

[7] Venkatram, Pranavram, et al. "Two-dimensional crystalline hard masks for high-aspect-ratio nanofabrication." Nature Materials 25.5 (2026): 737-746.

Keywords

Nanofabrication, dry etching, hard mask, etching selectivity, high-aspect-ratio, pattern transfer.

TPOC-1-PoC

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