Non-Volatile Memory for Extreme Environments: SBIR

OUSD (R&E) critical technology area(s): Advanced Computing and Software, Advanced Materials, Space Technology

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

Objective: Develop and demonstrate a co-packaged temperature-hard (-269°C to +600°C) and radiation-tolerant NOR Flash memory system for extreme environment applications.

Description: DARPA seeks to enable high performance computing for DoW systems that must function in extreme environments. Nonvolatile memory is a bottleneck, even in commercial High-Performance Computing and Artificial Intelligence systems. This phenomenon is referred to as the ‘Memory Wall’, where processing speeds become limited by memory access time. While there has been extensive research in emerging technologies to overcome this barrier, no commercial technology has shown the ability to reliably function in both high temperature and high radiation environments.

Today's charge-trap based NVMs, magnetoresistive RAM (MRAM), and resistive RAM (RRAM), each have significant deficiencies that limit their use in extreme conditions. MRAM, which stores data using magnetic states rather than electrical charges, offers some inherent advantages in radiation-heavy environments. However, current MRAM technology is typically limited to an operating temperature of around 105°C, falling short of the requirement for some of the most demanding applications. RRAM is a promising technology that relies on the formation and rupture of conductive filaments. While it has shown some radiation hardness, RRAM can suffer from filament instability and variable resistance when exposed to radiation, leading to unreliable performance.

The ideal NVM for extreme environments would possess several key characteristics:

• Inherent radiation hardness: the fundamental storage mechanism should be resistant to the effects of ionizing radiation, minimizing the need for heavy and power-consuming shielding.
• Wide temperature range: the memory must be able to operate reliably across a vast temperature range, from the cold of deep space to the heat of a nuclear reactor.
• High endurance and retention: the memory must be able to withstand a high number of read and write cycles and retain data for long periods without power.
• Low power consumption: power is a precious resource in space and other remote applications, so the memory must be highly energy efficient.

This SBIR program seeks demonstration of a non-volatile memory device that is resistant to extreme temperatures and radiation as a critical enabler for future advancements in space exploration, nuclear energy, and strategic defense. The radiation hardened memory should have an operating temperature range of -269C to 600C with a density of at least 1Mb, and operating frequency of 10MHz.

Due to the broad and dual-use nature of Complementary Metal-Oxide-Semiconductor (CMOS) technologies, security classification and export control requirements vary significantly based on the specific node, fabrication process and intended end-use. Proposers are solely responsible for determining the appropriate security classification of their proposed effort. If the memory system makes use of CMOS (i.e. for peripheral control logic), proposers must consider and describe the impacts of relevant DoW Security Classification guides to the proposed work.

Phase I

This topic solicits Direct to Phase II (DP2) proposals only. Proposers must provide data demonstrating that the following has been achieved outside of the SBIR program: (1) initial hardware demonstration of proposed memory technology (2) simulated and/or experimental data that support the feasibility of temperature-hard radiation tolerant memory system capable of meeting SBIR program metrics.

Phase II

Phase II will cover the fabrication of temperature-hard and radiation-tolerant non-volatile memory system capable of operating in extreme environments. Realized designs should incorporate both the non-volatile memory array and necessary peripheral control logic, demonstrating the ability to function reliably across the full -250°C to +600°C temperature envelope. In addition to meeting the extreme environmental survivability requirements specified, the prototype system should achieve a density of at least 32Mb and maintain an operating frequency of >1MHz. A packaging and integration report should be included to outline the methods and constraints for co-packaging the extreme-environment memory cells with CMOS or alternative control logic while mitigating thermal and radiation degradation. As Phase II is focused on fabrication and testing, milestones include interim reports on individual memory cell performance, test plans and initial radiation exposure results as the project proceeds toward final system assembly. By the end of Phase II, the performers must deliver ten packaged 32Mb memory prototype units meeting the program metrics and a final program report detailing the fabrication process, radiation survivability, and characterization data for delivered prototypes. All prototypes should be provided with adequate instructions and interface boards to support government testing and evaluation using standard environmental and radiation laboratory equipment.

Table 1 SBIR Phase II Metrics

Fixed payable milestones for this 24-month program should include:

• Month 1: Report detailing program plan and detailed technical design.
• Month 3: Quarterly report describing progress of technical work.
• Month 6: First test chip released to fabrication. The initial test chip can feature test structures or functional device.
• Month 9: Report detailing baseline performance of initial test chip.
• Month 12: Interim report describing progress of technical work, including results of radiation and/or temperature testing of first test chip.
• Month 15: Test plan outlining temperature, radiation and performance characterization of integrated device.
• Month 18: Integrated device released to fabrication.
• Month 21: Report detailing results of radiation, temperature and performance characterization of device addressing program metrics in Table 1.
• Month 24: Final report summarizing design, work undertaken, results, and comparison with alternative state-of-the-art systems; 10 prototype units with interface boards; Test instructions.

Phase III dual use applications

Phase III work is typically oriented towards commercialization of SBIR/STTR research or technology with funding obtained from either the private sector, a non-SBIR/STTR Government source, or both, to develop the technology into a viable product for sale in military or private sector markets. Given the needs for resilient non-volatile memory technology in space, nuclear and strategic defense technologies, this SBIR has potential dual-use applicability across DoD and commercial entities. These systems require advanced capabilities with high degrees of reliability given the cost of failure.

References

[1] Hellenbrand, M., Teck, I. & MacManus-Driscoll, J.L. Progress of emerging non-volatile memory technologies in industry. MRS Communications 14, 1099–1112 (2024). https://doi.org/10.1557/s43579-024-00660-2

[2] Skowronski, M. Material instabilities in the TaOx-based resistive switching devices (Invited). 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023. pp. 1-5. https://doi.org/10.1109/IRPS48203.2023.10117796

[3] Worledge, D.C., Hu, G. Spin-transfer torque magnetoresistive random access memory technology status and future directions. Nat Rev Electr Eng 1, 730–747 (2024). https://doi.org/10.1038/s44287-024-00111-z

Keywords

Extreme environment electronics, radiation-hardened, temperature-hardened, nonvolatile memory, microelectronics, memory devices

TPOC-1-PoC

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