The unrelenting progression of Moore's Law has created a steady cadence to ever-smaller transistors and more powerful chips, allowing billions of transistors to be integrated on a single system-on-chip (SoC). However, engineering productivity has not kept pace with Moore's Law, leading to prohibitive increases in development costs and team sizes for leading-edge SoC design. To help manage the complexity of SoC development, design reuse in the form of Intellectual Property (IP) modules has become the primary strategy. IP modules are pre-designed, functional circuit blocks that are similar in nature to software library functions and are developed internally by an organization or procured from an external, third-party IP vendor.
Defense systems today may leverage over a hundred unique IP blocks, which creates significant productivity improvements but also limits visibility into the final SoC’s behavior and offers no clear path for complete security or integrity verification due to schedule and cost pressures. Further, the single layer point-to-point approach associated with the current IP licensing model limits the scope of reuse and abstraction.
A candidate approach for creating a deeply layered, transparent SoC development model is to draw from best practices in the software community and leverage open source hardware IP. However, the idea of reusing the open source IP available today has not seen wide adoption due to the high cost of failure, limited capabilities, and inability to prove functionality prior to adoption.
To help address the current design complexity challenges, the Posh Open Source Hardware (POSH) program seeks to enable mathematically provable secure electronics and create an open source hardware IP ecosystem, along with accompanying validation tools. Under the program, researchers will work to develop methodologies, standards, and simulation as well as emulation technologies for the verification and mathematical inspection of analog and digital IP to provide proof of functionality and security. The program also aims to develop and release a number of silicon-proven analog and digital IP blocks on an open source platform to serve as a foundation for rapid design of complex secure SoCs at leading edge technology nodes.
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