Next-generation intelligent systems supporting Department of Defense (DoD) applications like artificial intelligence, autonomous vehicles, shared spectrum communication, electronic warfare, and radar require processing efficiency that is orders of magnitude beyond what is available through current commercial electronics. Reaching the performance levels required by these DoD applications however will require developing highly complex system-on-chip (SoC) platforms that leverage the most advanced integrated circuit technologies. Despite advances in electronic design automation (EDA) tools, the complexity associated with the design and verification of integrated circuits (ICs) continues to increase rapidly due in part to the steady progress of Moore's Law. To help meet design requirements, commercial electronics manufacturers creating advanced hardware solutions will employ large teams of designers, each with expertise in a specific facet of the design flow. For the DoD however, researchers and development teams do not have the resources available to effectively execute such a strategy, resulting in hardware design cycles that are two to three times longer than commercial establishments.
To overcome the design expertise gap and keep pace with the exponential increase in chip complexity, the Intelligent Design of Electronic Assets (IDEA) program seeks to develop a general purpose hardware compiler for no-human-in-the-loop translation of source code or schematic to physical layout (GDSII) for SoCs, System-In-Packages (SIPs), and Printed Circuit Boards (PCBs) in less than 24 hours. The program aims to leverage advances in applied machine learning, optimization algorithms, and expert systems to create a compiler that could allow users with no prior design expertise to complete physical design at the most advanced technology nodes. The goal of the IDEA program is to provide the DoD with a path to rapid development of next-generation electronic systems without the need for large design teams, reducing the cost and complexity barriers associated with leading-edge electronic design.
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