Precise timing is essential across DoD systems, including communications, navigation, electronic warfare, intelligence systems reconnaissance, and system-of-systems platform coordination, as well as in national infrastructure applications in commerce and banking, telecommunications, and power distribution. Improved clock performance throughout the timing network, particularly at point-of-use, would enable advanced collaborative capabilities and provide greater resilience to disruptions of timing synchronization networks, notably by reducing reliance on satellite-based global navigation satellite system (GNSS) timing signals. The Atomic Clock with Enhanced Stability (ACES) program aims to develop next-generation, battery-powered chip-scale atomic clocks (CSAC) with 1000X improvement in key performance parameters compared to existing CSAC technology.
First-generation CSACs, developed under prior DARPA programs, are now available commercially and have demonstrated the feasibility and value of CSAC technology across DoD and civilian applications. These devices offer unprecedented timing stability within their domain of size, weight, and power (SWaP), but their performance is fundamentally limited—particularly in the key performance metrics of temperature sensitivity (tempco), long-term frequency aging, and turn-on to turn-on reproducibility (retrace)—due to the physics associated with the design of these devices.
The ACES program is exploring alternative CSAC physics architectures with the objective of demonstrating a CSAC with 1000X improvement in tempco, aging, and retrace. The program includes engineering efforts to demonstrate SWaP reduction of laboratory-proven atomic clock technologies and to deliver ACES prototype clocks. The program also includes basic research efforts to explore novel component technologies and alternative physics approaches that have the potential to substantively impact future ACES clock architectures.
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