Program Summary
Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge. However, developing an effective 3D SoC stack would require increasing the width of buses to memory through much finer pitch interconnects, while simultaneously decreasing the resistor-capacitor (RC) delays through much shorter interconnect lines in the SoC
To address the memory bottleneck problem, the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program seeks to develop the monolithic 3D technology required to build logic, memory, and input/output (I/O) on a single die using a legacy lithography node while improving performance by more than 50X when compared with leading edge technology nodes. To achieve its goals, 3DSoC seeks to develop fabrication technology as well as the design flows required to take advantage of the technology’s capabilities.
The 3DSoC program aims to drive the future of computation architecture, removing the limitations of the current 2D approach to SoC design and manufacturing. The resulting fabrication technology is intended to be based at a U.S. manufacturing facility, which will allow Department of Defense (DoD) entities to have easy access to the technology, tools, and manufacturing capabilities to explore and build future computation systems that will deliver 50X better performance at power results and improve the performance of future DoD systems.