Program Summary
The unlimited demand for more devices at higher speeds ensures that the future wireless spectrum will be increasingly crowded and complex. A promising way to deal with this complexity is RF (radio frequency) autonomy, where radios use artificial intelligence (AI) to sense the spectrum and adapt to the perceived environment. Compared to human-managed systems, RF autonomy can increase robustness to interference and improve the capacity of the spectrum to accommodate more devices.
The edge processors of choice for today’s autonomous radios are field programmable gate arrays (FPGAs). However, signal environments can change far faster (nanoseconds) than FPGAs can be reprogrammed (milliseconds). Realizing the benefits of RF autonomy across wide bandwidths – particularly when the spectrum may contain novel AI-designed signals – requires new classes of receiver processors.
DARPA’s Processor Reconfiguration for Wideband Spectrum Sensing (PROWESS) program aims to develop high-throughput, streaming-data processors that reconfigure in real time to detect and characterize novel signals. Through processors that self-reconfigure within 50 nanoseconds, PROWESS will enable “just-in-time” synthesis of processing pipelines in uncertain environments. PROWESS will allow future receivers to optimize performance to both measured spectrum conditions and the needs of cognitive RF decision logic.
PROWESS combines parallel reconfigurable processing arrays with multi-stage software schedulers/compilers to develop run-time reconfigurable processors with 200 giga-operations per second per square millimeter (GOPS/mm2) compute density and 50 nanosecond program switch time. PROWESS eliminates dark silicon (achieving 90% device utilization) and seeks to achieve a 40x increase in signal throughput relative to fixed processing pipelines.
PROWESS development spans two phases. The goal of the ongoing Phase 1 is to mature processor designs through a preliminary design review (PDR) grounded in risk reduction experimentation. This PDR is anticipated to include both device and software design elements and reflect a design of sufficient maturity to support device tapeout early in Phase 2. The goal of Phase 2 will be to mature processor designs through a critical design review (CDR) and demonstrate prototype processor devices on streaming digital data representative of challenging RF environments. Additionally, a potential Phase 3 is under consideration to integrate future PROWESS devices with prototype RF receivers.