DARPA Electronics Resurgence Initiative

On June 1, 2017, the DARPA Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) to ensure far-reaching improvements in electronics performance well beyond the limits of traditional scaling. The ERI will draw on new and existing DARPA programs to make a significant investment into enabling circuit specialization and managing complexity. Building on the tradition of other successful government-industry partnerships, the ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD.

Moore’s Law, defined on pages one and two of Gordon Moore’s seminal 1965 paper entitled “Cramming More Components onto Integrated Circuits,” has guided the electronics industry for more than 50 years. The continued realization of this Law, however, is challenged on both technical and economic grounds. Page three of Moore’s paper described research areas required to manage this possibility. As part of the ERI and in deference to Moore’s ideas, MTO’s ERI Page 3 Investments will support research and development in each of these areas: Architectures, Design, and Materials and Integration. To fully unlock microelectronics innovation and maintain DoD’s technical superiority, programs within these Page 3 thrust areas will foster the environment needed for the next wave of U.S. semiconductor advancement.

Each thrust area will support two separate programs that operate independently of each other.

Architectures: Can we enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software/hardware co-design?

• The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms. SDH will create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time, or single application limitations associated with ASIC development.    
• The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device.    

Design: Can we dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation?

• The overall goal of the Intelligent Design of Electronic Assets (IDEA) program is to create a “no human in the loop” layout generator that enables users with no electronic design expertise to complete the physical design of electronic hardware within 24 hours. IDEA will develop the algorithms, methodologies, and software required to create an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards.    
• The overall goal of the Posh Open Source Hardware (POSH) program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs. POSH seeks to create the hardware assurance technology required for signoff-quality validation of open source mixed signal SoCs, develop critical open source IP components, and demonstrate a high-performance open source SoC using the POSH ecosystem.

Materials & Integration: Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

• The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities.    
• The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures.

ERI aims to more constructively enmesh the technology needs and capabilities of the defense enterprise with the commercial and manufacturing realities of the electronics industry. To facilitate collaboration between defense and commercial entities, DARPA will publish a regularly updated list of groups interested in teaming on proposals or research. Links to the BAAs and other proposal resources are located in the resources column.

The ERI Page 3 Investments are the next steps in creating a national electronics capability that will provide a foundational contribution to U.S. economic and national security interests. DARPA is eager to work collaboratively with entities that will further the broader cause of the electronics industry while simultaneously advancing national defense.

To jump-start innovation and foster forward-looking collaborations across the U.S. electronics community, DARPA will host an ERI Summit over three days, bringing together those most impacted by the coming inflection in Moore’s Law. For more information, please visit: www.ERI-summit.com

For general inquiries, including eligibility and participation, please reach out to ERI_page3@darpa.mil. Media questions and requests should be directed to outreach@darpa.mil.