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The Automatic Implementation of Secure Silicon (AISS) program aims to ease the burden of developing secure chips. AISS seeks to create a novel, automated chip design flow that will allow security mechanisms to scale consistently with the goals of a chip design. The target design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security trade-off. The target system on chip (SoC) – will be automatically generated, integrated, and optimized, and will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased.