Defense Advanced Research Projects AgencyTagged Content List

Foundational Strategic Technologies and Systems

Versatile enabling technologies that could lead to entire new classes of capabilities

Showing 24 results for Tech-Foundations + Complexity RSS
August 2-3, 2017,
DARPA Conference Center
The Defense Advanced Research Projects Agency (DARPA) Strategic Technology Office (STO) is hosting a “Sync with STO” event on August 2 – 3, 2017. The purpose of the event is to (1) familiarize attendees with STO’s vision, problem spaces, program managers (PMs), and technology interests; and (2) facilitate technical discussions between STO PMs and attendees that explore innovative and impactful solution ideas for strategic national security challenges. The event is scheduled for August 2 – 3, 2017, at the DARPA Conference Center located at 675 N. Randolph St. Arlington, VA 22203.
The general-purpose computer has remained the dominant computing architecture for the last 50 years, driven largely by the relentless pace of Moore’s Law. As this trajectory shows signs of slowing, however, it has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures. Today’s specialized, application-specific integrated circuits (ASICs) — hardware customized for a specific application — offer limited flexibility and are costly to design, fabricate, and program.
Next-generation intelligent systems supporting Department of Defense (DoD) applications like artificial intelligence, autonomous vehicles, shared spectrum communication, electronic warfare, and radar require processing efficiency that is orders of magnitude beyond what is available through current commercial electronics. Reaching the performance levels required by these DoD applications however will require developing highly complex system-on-chip (SoC) platforms that leverage the most advanced integrated circuit technologies.
Due to engineering limitations and cost constraints, the dynamics of the electronic industry are continually changing. Commercial companies increasingly recognize the need to differentiate their products through research in areas other than device scaling, such as new circuit architectures and computing algorithms.
The unrelenting progression of Moore's Law has created a steady cadence to ever-smaller transistors and more powerful chips, allowing billions of transistors to be integrated on a single system-on-chip (SoC). However, engineering productivity has not kept pace with Moore's Law, leading to prohibitive increases in development costs and team sizes for leading-edge SoC design. To help manage the complexity of SoC development, design reuse in the form of Intellectual Property (IP) modules has become the primary strategy.