Defense Advanced Research Projects AgencyTagged Content List

Size, Weight and Power Constraints

Making technologies smaller, lighter and more power-efficient to increase military effectiveness

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Most people are familiar with the concept of RADAR. Radio frequency (RF) waves travel through the atmosphere, reflect off of a target, and return to the RADAR system to be processed. The amount of time it takes to return correlates to the object’s distance. In recent decades, this technology has been revolutionized by electronically scanned (phased) arrays (ESAs), which transmit the RF waves in a particular direction without mechanical movement. Each emitter varies its phase and amplitude to form a RADAR beam in a particular direction through constructive and destructive interference with other emitters.
Phased radio frequency (RF) arrays use numerous small antennas to steer RF beams without mechanical movement (think radar without a spinning dish). These electronics are invaluable for critical DoD applications such as radar, communications and electronic warfare. Their lack of moving parts reduces maintenance requirements and their advanced electromagnetic capabilities, such as the ability to look in multiple directions at once, are extremely useful in the field. These benefits, though, come with a high price tag. Current phased arrays are extremely expensive and can take many years to engineer and build.
Today’s electromagnetic (EM) systems use antenna arrays to provide unique capabilities, such as multiple beam forming and electronic steering, which are important for a wide variety of applications such as communications, signal intelligence (SIGINT), radar, and electronic warfare.
The explosive growth in mobile and telecommunication markets has pushed the semiconductor industry toward integration of digital, analog, and mixed-signal blocks into system-on-chip (SoC) solutions. Advanced silicon (Si) complementary metal oxide semiconductor (CMOS) technology has enabled this integration, but has also led to a rise in costs associated with design and processing. Driven by aggressive digital CMOS scaling for high-volume products, Intellectual Property (IP) reuse has emerged as a tool to help lower design costs associated with advanced SoCs.
Complex Defense systems, such as RADAR, communications, imaging and sensing systems rely on a wide variety of microsystems devices and materials. These diverse devices and materials typically require different substrates and different processing technologies, preventing the integration of these devices into single fabrication process flows. Thus, integration of these device technologies has historically occurred only at the chip-to-chip level, which introduces significant bandwidth and latency-related performance limitations on these systems, as well as increased size, weight, power, and packaging/assembly costs as compared to microsystems fully integrated on a single chip.