Defense Advanced Research Projects AgencyTagged Content List

Information Microsystems

Relating to computer and other digital electronic systems

Showing 14 results for Microsystems + Processing RSS
Radio Frequency and mixed signal electronics face performance limitations due to the limited circuit complexity possible in typical high-speed/high-dynamic-range compound semiconductor integrated circuit technologies. By integrating these high-performance electronics with deep submicron silicon complementary metal-oxide semiconductor (Si CMOS) technology, designers can exploit the ultra large scale integration density of Si CMOS to combine complex signal processing and self-correction architectures with the highest performance compound semiconductor electronics, thus achieving unprecedented levels of performance (e.g. bandwidth, dynamic range, power consumption).
High performance optoelectronic systems, e.g. ultra low-noise lasers and optoelectronic signal sources, are employed in numerous applications such as fiber optic communications, high-precision timing references, LADAR, imaging arrays, etc. Current state-of-the-art ultra-low noise lasers and optoelectronic signal sources use macro-scale photonics for mechanical and thermal noise suppression, and off-chip electronics for feedback control. The benchtop or rack mount component-level assembly of these sources limits photonic coupling efficiency as well as the speed of electronic feedback, and also adds size and weight to the system. Integration of these components in a chip-scale form factor could greatly mitigate these limitations.
The DAHI Foundry Technology program thrust seeks to establish an accessible, manufacturable technology for device-level heterogeneous integration of a wide array of materials and devices (including, for example, multiple electronics and MEMS technologies) with complex silicon-enabled (e.g. CMOS) architectures on a common silicon substrate. of The DAHI Foundry Technology thrust will incorporate and build upon the heterogeneous integration technologies of the COSMOS and E-PHI program thrusts, while also developing new capabilities in heterogeneous integration processes, yield and circuit design innovation. 
Program Manager
Dr. Randy Garrett joined DARPA in February 2019 as a program manager in the Strategic Technology Office. Prior to arriving at DARPA, he worked for commercial cybersecurity companies.
The POEM program aims to address electrical communications link limitations by developing chip-scale, integrated photonic technology to enable seamless intrachip and offchip photonic communications that provide the required bandwidth with low energy/bit. The POEM program will exploit wavelength division multiplexing (WDM), allowing much higher bandwidth capacity per link, which is imperative to meeting the communication needs of future microprocessors. Such a capability would propel the microprocessor onto a new performance trajectory and impact the actual runtime performance of DoD-relevant computing tasks for power-starved embedded applications and supercomputing.