Defense Advanced Research Projects AgencyTagged Content List

Microchips and Components

Relating to miniaturized electronic circuitry and its components and features

Showing 24 results for Microchips + Tech-Foundations RSS
Driven by the rapidly evolving national security threat landscape, future defense systems will need access to low size, weight, and power (SWaP) artificial intelligence (AI) solutions that can rapidly transition from idea to practice. In recent years, the ability to learn from large datasets has advanced significantly due to increases in hardware performance, advances in machine learning (ML) algorithms, and the availability of high quality open datasets.
In modern warfare, decisions are driven by information. That information can come in the form of thousands of sensors providing information, surveillance, and reconnaissance (ISR) data; logistics/supply-chain and personnel performance measurements; or a host of other sources and formats. The ability to exploit this data to understand and predict the world around us is an asymmetric advantage for the Department of Defense (DoD).
Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge.
08/30/2017
In June 2017, DARPA announced the Electronics Resurgence Initiative (ERI) as a bold response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore’s Law, prompting a need for alternative approaches to traditional transistor scaling.