Defense Advanced Research Projects AgencyTagged Content List


A process or rule set used for calculations or other problem-solving operations

Showing 19 results for Algorithms + Electronics RSS
The unrelenting progression of Moore's Law has created a steady cadence to ever-smaller transistors and more powerful chips, allowing billions of transistors to be integrated on a single system-on-chip (SoC). However, engineering productivity has not kept pace with Moore's Law, leading to prohibitive increases in development costs and team sizes for leading-edge SoC design. To help manage the complexity of SoC development, design reuse in the form of Intellectual Property (IP) modules has become the primary strategy.
In modern warfare, decisions are driven by information. That information can come in the form of thousands of sensors providing information, surveillance, and reconnaissance (ISR) data; logistics/supply-chain and personnel performance measurements; or a host of other sources and formats. The ability to exploit this data to understand and predict the world around us is an asymmetric advantage for the Department of Defense (DoD).
Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge.
In June 2017, DARPA announced the Electronics Resurgence Initiative (ERI) as a bold response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore’s Law, prompting a need for alternative approaches to traditional transistor scaling.