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For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices.
April 10, 2019, 9:00 AM EDT,
DARPA Conference Center
The Microsystems Technology Office is holding a Proposers Day meeting to provide information on our new Automatic Implementation of Secure Silicon (AISS) program. AISS will address the economic and technical challenges associated with building in chip security. The program aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs, and maximize design productivity. The objective is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open-source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive.