Defense Advanced Research Projects AgencyTagged Content List

Inverting Cost Equation

Imposing higher costs on adversaries

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A once highly manual process, circuit design has been transformed by the advent of electronic design automation (EDA) tools and modular design methodologies. Despite continuing advances in automation technologies, the demand for increasingly complex System-on-Chip (SoC) platforms has shown no sign of slowing. Today’s SoCs incorporate billions of transistors with miles of electrical wiring that are integrated within a tiny chip.
The general-purpose computer has remained the dominant computing architecture for the last 50 years, driven largely by the relentless pace of Moore’s Law—the transistor-scaling that has allowed for a half-century of rapid progress in electronics. As this trajectory shows signs of slowing, however, it has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures.
The use of intellectual-property (IP) blocks–discrete, modular, reusable blocks that deliver frequently used circuit functions—has significantly streamlined the design and creation of microchips. Just as the number of transistors per chip has grown dramatically in line with Moore’s Law—the transistor scaling that has allowed for 50 years of electronics advancement–so too has the number of IP blocks on those same chips.
First announced in June 2017, DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5B investment in the future of domestic electronic systems – is rolling out the second phase of its research priorities. Comprised of several ongoing DARPA programs – including the six recently awarded ERI “Page 3” programs –ERI addresses long-foreseen obstacles to Moore’s Law and the challenges impeding 50 years of rapid progress in electronics advancement. The next phase of ERI will focus on further enmeshing the technology needs and capabilities of the defense enterprise with the commercial and manufacturing realities of the electronics industry.
DARPA has narrowed the potential launch locations for the DARPA Launch Challenge to eight, with options for both vertical and horizontal launch. The challenge will culminate in late 2019 with two separate launches to low Earth orbit within weeks of each other from two different sites. Competitors will receive information about the final launch sites, payloads, and targeted orbit in the weeks prior to each launch.