Defense Advanced Research Projects AgencyTagged Content List

Inverting Cost Equation

Imposing higher costs on adversaries

Showing 21 results for Cost + Manufacturing RSS
Due to engineering limitations and cost constraints, the dynamics of the electronic industry are continually changing. Commercial companies increasingly recognize the need to differentiate their products through research in areas other than device scaling, such as new circuit architectures and computing algorithms.
The unrelenting progression of Moore's Law has created a steady cadence to ever-smaller transistors and more powerful chips, allowing billions of transistors to be integrated on a single system-on-chip (SoC). However, engineering productivity has not kept pace with Moore's Law, leading to prohibitive increases in development costs and team sizes for leading-edge SoC design. To help manage the complexity of SoC development, design reuse in the form of Intellectual Property (IP) modules has become the primary strategy.
In modern warfare, decisions are driven by information. That information can come in the form of thousands of sensors providing information, surveillance, and reconnaissance (ISR) data; logistics/supply-chain and personnel performance measurements; or a host of other sources and formats. The ability to exploit this data to understand and predict the world around us is an asymmetric advantage for the Department of Defense (DoD).
The capabilities and technical specifications required for Department of Defense (DoD) platforms are constantly changing due to unanticipated circumstances, needs and emerging threats. However, complex development and design cycles and the associated high costs of structural design changes for current technologies significantly limit our ability to rapidly and affordably evolve such systems.
Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge.