Defense Advanced Research Projects AgencyTagged Content List

Harnessing Complexity

Systems comprising multiple and diverse interactions

Showing 38 results for Complexity + Programs RSS
In modern warfare, decisions are driven by information. That information can come in the form of thousands of sensors providing information, surveillance, and reconnaissance (ISR) data; logistics/supply-chain and personnel performance measurements; or a host of other sources and formats. The ability to exploit this data to understand and predict the world around us is an asymmetric advantage for the Department of Defense (DoD).
Cyber physical systems (CPS) are instrumental to current and future Department of Defense (DoD) mission needs – unmanned vehicles, weapon systems, and mission platforms are all examples of military-relevant CPS. These systems and platforms integrate cyber and physical subsystems, and the enormous complexity of the resulting CPS has made their engineering design a daunting challenge. An immediate consequence of this complexity is development cycles with prolonged timelines that challenge DoD’s ability to counter emerging threats.
The capabilities and technical specifications required for Department of Defense (DoD) platforms are constantly changing due to unanticipated circumstances, needs and emerging threats. However, complex development and design cycles and the associated high costs of structural design changes for current technologies significantly limit our ability to rapidly and affordably evolve such systems.
Military and civilian organizations have deep interest in human performance optimization (HPO). A key challenge for optimizing human performance, however, is the “tyranny of averages:” a common experimental approach that uses between-subject outcomes and group averages (means) to make conclusions about the efficacy of a given intervention.
Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge.