Advances in integrated circuit technologies have enabled single-chip integration of multiple analog/RF and digital functions, resulting in complex mixed-signal systems-on-a-chip (SoCs) well suited for meeting the stringent and unique requirements of DoD electronic microsystems. High performance SoC designs have been made feasible by the increased speed and higher density available in modern nanometer-scale integrated circuit processes. However, a major consequence of the drive toward ever smaller transistor gate lengths is an exponential increase in intrawafer and intradie process variations that degrade on circuit performance. Consequently, designers must over-constrain performance order to guarantee sufficient postfabrication performance yield.
The goal of the Self-HEALing Mixed-Signal Integrated Circuits (HEALICs) program is to regain this lost performance by adding sensing and control circuitry that will compensate for the process, environmental, and ageing variations in situ, which will ultimately allow designers to focus on performance goals and not on yield-related issues. This initiative is not limited to any particular type of circuit or control approach; rather, it aims to develop techniques and technologies that allow any mixed-signal design to be runtime-corrected at the SoC level. The technologies developed under this program also have the potential to significantly enhance the long-term reliability of DoD electronic systems.
HEALICs performers will demonstrate their self-healing control algorithms and circuitry on a complex, mixed-signal baseline SoC design that was determined to be impractical due to processing technology variability or was realized with extremely poor (near zero) performance yield as measured by target performance metrics. The program goals are to demonstrate that, upon the activation of this on-chip healing circuitry, the performance yield of their baseline SoC can be dramatically increased to greater than 95 percent with less than a 5 percent increase in power consumption and low impact on overall chip area.
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