The objective of the Compound Semiconductor Materials on Silicon (COSMOS) program is to develop a viable process for the fine-scale heterogeneous integration of compound semiconductor (CS) devices within standard Si complementary metal oxide semiconductor (CMOS) technology and to establish that this integration enables superior performance in specific mixed-signal circuit demonstrators. The CS devices provide much higher speed-breakdown voltage product (Johnson Figure of Merit) than CMOS transistors, whereas modern CMOS technology provides unprecedented integration density/complexity for computation and signal processing functions. The COSMOS program offers designers the potential to exploit the "best junction for the function." The program will focus on four major technical areas of interest: assembly and integration technologies, thermal management, design methodologies, and yield enhancement. COSMOS will culminate in the demonstration of a heterogeneously integrated 16-bit analog-to-digital converter. Device level goals include assembling CS and Si-based transistors in less than or equal to 5µm minimum proximity, with less than or equal to 5µm minimum pitch of the heterogeneous interconnect vias and yield of greater than or equal to 99.99 percent of the heterogeneous interconnects. The heterogeneously integrated devices should operate with minimal change in performance from that of the original devices in their native homogeneous technologies.
The COSMOS program is structured in three phases. Phase 1 developed a viable process technology to integrate CS and Si CMOS transistors on a very short size-scale within a small circuit (transistor-scale integration technology). The specific circuit demonstrator to validate performance will be a standard differential amplifier, consisting of five transistors. Phase 2 focuses on yield enhancement and circuit integration. The objectives of this phase are to significantly improve both yield and density of the heterogeneous interconnect process, the latter achieved through a significant reduction in the pitch of the heterogeneous interconnects. The overall goal of this phase will be to demonstrate a heterogeneously integrated 13-bit digital-to-analog converter (DAC) achieving 78 dBc of spur free dynamic range (SFDR) at 1 GHz output frequency. In Phase 3, the COSMOS process will be scaled to a much more complex circuit, a heterogeneously integrated, 16-bit analog-to-digital converter that will support 98 dBc of SFDR across a 500-MHz bandwidth. Ultimately, it is envisioned the COSMOS technology will be made available to the DoD design community as a high-yield foundry technology.
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