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Technology for Frequency Agile Digitally Synthesized Transmitters (TFAST)

Program Manager: Dr. Sanjay Raman

The Department of Defense (DoD) focuses on a wide array of applications for high-performance mixed-signal (combined analog and digital) circuits. The Technology for Frequency Agile Digitally Synthesized Transmitters (TFAST) program's ultimate goal is to develop high frequency digital synthesizer and related circuits with high dynamic range, low phase noise, low direct current (DC) power, and wide bandwidth. The preferred transistor technology for such circuits needs to have extremely high speed (high unity cut off frequency, F_t, and high maximum frequency of oscillation, F_max), high breakdown, low phase noise, and low power. Heterojunction bipolar transistors (HBTs) generally lattice-matched to indium phosphide (InP) offer the best combination of carrier transport and electrical breakdown but have been restricted by a lack of a truly scalable device topology and processing approach. Additionally, mesa-based InP HBT technology is limited in the achievable level of integration (defined as transistors per circuit) to <5000 transistors (Figure 1).

The TFAST program is addressing all aspects of the development from materials, device design, device processing, circuit analysis, interconnects, and integration in two phases. Phase I is a technology push effort to establish a viable super-scaled InP HBT that is more planar, lower power and capable of integration levels of 20,000 transistors and above (Figure 2).  Phase II is an extension of Phase I, dependent on the success of Phase I, that will demonstrate complex mixed-signal circuits.

For the Phase I effort, the milestones include: pushing the emitter feature size down by a factor of two to three beyond that projected for next generation; fully fully scaled, mesa-based InP HBTs; extending F_t/F_max by approximately a factor of two over current production devices while maintaining a suitably high (e.g. 4V) breakdown voltage; increasing the current density over conventional approaches by a factor of three to five at an appropriately low operating voltage (e.g. < 1.5 V); and demonstrating the core circuit technology (e.g. static flip-flops or dividers) at speeds two to three times faster than the current state-of-the-art (Table 2, Figure 3).

The Phase II effort will extend the Phase I development to the realization of complex (transistor counts > 20,000) mixed-signal circuits employing super-scaled InP HBTs. Specific efforts will be put towards direct digital frequency synthesizers that advance the state-of-the-art by a factor of three in clock frequency with high spur-free dynamic range over a large bandwidth.