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Radiation Hardening by Design (RHBD)
Program Manager: Dr. Carl McCants
The objective of the Radiation Hardening by Design (RHBD) program is to develop and demonstrate design and layout techniques to support the fabrication of strategically radiation hardened integrated circuits from pure design approaches; no changes in fabrication or materials. The program is focused on foundry-type silicon technologies, ultra-deep submicron (e.g. < 90 nm technology) geometries, and digital / analog / mixed signal integrated circuits. Specific interest is in the demonstration of design techniques for producing radiation hardened devices on standard commercial foundry flows, without any modification of the existing process or violation of design and layout rules, with corresponding electrical performance and area penalties of less than or equal to one fabrication generation.
The first phase of this program was primarily concerned with demonstrating the efficacy of Radiation Hardening by Design (RHBD) from a technology stand point. Towards this end, both digital and analog devices and simple circuits were designed, fabricated and tested. Target foundry technologies as appropriate were 130 nm bulk silicon and 130 nm SiGe BiCMOS. This program has been partnering with the DoD Trusted Foundry Program for access to leading-edge semiconductor technologies and design libraries and designed circuit cores. Radiation performance criteria for the test structures of this phase are as follows:
Additionally, these radiation performance target values should be achieved with less than a one technology generation penalty in size, speed or power.
The next phase will refine the RHBD techniques and develop more accurate device models from the data generated in phase one and design and fabricate radiation hardened design cells, libraries, test structures and complex devices. Digital libraries will be exercised through the development of a demonstration processor chip with an ARM core which includes additional embedded instrumentation to improve observability of any radiation induced errors. Also a large static random access memory (SRAM) array will be fabricated. More complex integrated circuits may be fabricated based on technology performance and characteristics. Radiation and performance specifications remain the same as phase one.
In addition to the development of design libraries, the RHBD program will perform technology characterization of leading edge, deep sub-micro commercial processes. Test chips fabricated in 65 and 45nm will undergo a comprehensive set of measurements and tests for radiation characterization of single event upsets (SEU), single event transients (SET) and total ionizing dose (TID) hardness as well as RHBD-based mitigation approaches in a deep sub-micron commercial Silicon on insulator (SOI) process. A variety of circuit test structures will include transistor arrays with different shapes and operating voltages, basic input/output (I/O) and logic cells, ring oscillators, flip flops, self-heating and snapback test devices and SRAM arrays.