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Gratings of Regular Arrays and Trim Exposures (GRATE)
Program Manager and PoC: Dr. Michael Fritze
Document Type: Presolicitation
Solicitation Number: BAA10-12
Posted Date: December 18, 2009
Original Response Date: February 03, 2010
Current Response Date: February 03, 2010
Original Archive Date: December 31, 2010
Current Archive Date: December 31, 2010
Classification Code: A -- Research & Development
Naics Code: 541 -- Professional, Scientific, and Technical Services/541712 -- Research and Development in the Physical, Engineering, and Life Sciences (except Biotechnology)
Description
DARPA is soliciting innovative research proposals in the area of grating-based integrated circuit layout design and patterning. The goal of the Gratings of Regular Arrays and Trim Exposures (GRATE) program is to develop revolutionary new circuit design methodologies combined with grating-based lithography tools to enable cost effective low volume nanofabrication for Department of Defense (DoD) applications. The novel circuit design methodologies will enable simplified physical layout implementation of circuits by leveraging extremely regular geometries. Overall circuit densities and performance will not be sacrificed when utilizing these new design approaches. These simplified circuit design geometries will be implemented using ultra-high-resolution grating patterns which can be fabricated at high throughput using either mask-based or maskless (interference) lithography. Cost effective low volume microfabrication will be achieved by lowering the design and fabrication costs of custom application-specific integrated circuits (ASICs), enabling maskless interference-based patterning with practical throughputs, and improving fabrication yield resulting from regular circuit patterns. See the full DARPA-BAA-10-12 document attached.
Contracting Office Address
3701 North Fairfax Drive
Arlington, Virginia 22203-1714
Primary Point of Contact
Michael C. Fritze,
Program Manager, MTO
DARPA-BAA-10-12@darpa.mil