Computational capability is an enabler for nearly every military system, but increases in computational capability are limited by available system power and constraints on the ability to dissipate heat. This is a challenge for embedded applications such as soldier-borne applications, UAVs and command and control systems on submarines. Today’s intelligence, surveillance and reconnaissance (ISR) systems have sensors that collect far more information than they can process in real time; as a result, what could be invaluable real-time intelligence data in the hands of our warfighters is simply discarded, or perhaps recorded and processed hours or days after it was collected.
Such computational capabilities could be improved if the amount of computation that can be performed per watt were increased. Currently, power efficiencies of around one billion floating point operations per second per watt (1 GFLOPS/W) are observed at the processing system level. Examples show we need at least 50 GFLOPS/W, and requirements of at least 75 GFLOPS/W can be confidently anticipated. Extrapolating current processing trends suggests that we will not achieve the processing performance required to exploit our data streams.
The goal of DARPA’s Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program is to seek revolutionary approaches and to research and develop the technologies and techniques that will provide the power efficiency required to enable embedded computing systems. The PERFECT program addresses seven program elements. Five of these, Architecture, Concurrency, Resilience, Locality, and Algorithms, comprise the primary research thrusts, and the remaining two, Simulation and Test and Validation, are essential support activities. This combination of technologies coupled with anticipated industry fabrication geometry advances to 7 nm is intended to enable the PERFECT program to attain 75 GFLOPS/W, one of the PERFECT program’s goals as stated in the original PERFECT Broad Agency Announcement.
The PERFECT program will be performed over three phases. Phase 1 will initiate concept development and provide initial proof of impact on processing power efficiency. Phase 2 will develop the technology and techniques to obtain overall processing system improvement of 75 times greater processing power efficiency. The PERFECT program is not physically building processing hardware, rather it seeks to measure and demonstrate progress via simulation and limited supporting test devices. Phase 3 will develop the most promising technologies and provide a path to implementation. The impact of the PERFECT program will be to make far more computing capability available in embedded systems within the electrical power constraints. The PERFECT program seeks to greatly increase the power-efficiency of deployed embedded systems, providing greater computational capability, and thereby providing greater military effectiveness.
Dr. Joseph Crossjoseph.firstname.lastname@example.org